Optimization of Active Geometry Configuration and Shallow Trench Isolation (STI) Stress for Advanced CMOS Devices
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概要
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Mechanical stress induced by active geometry is optimized for minimum variation of complementary metal oxide semiconductor (CMOS) electrical characteristics with varying active profiles. In this study, wafers with two different shallow trench isolation (STI) stress levels were investigated. By co-optimizing the active profile and STI stress level of model test structures, less than 3% device deviation is achieved when compared with simulation program with integrated circuit emphasis (SPICE) model in the full breadth of N channel and P channel metal oxide semiconductor (N/PMOS) geometry.
- 2004-04-15
著者
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Jung Le-tien
United Microelectronics Corp. Specialty Technology Department Technogoly & Process Development D
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Kuo Chien-li
United Microelectronics Corporation (umc) Central R&d Division
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Chen J.
United Microelectronics Corp. Logic Technology Department Technology & Process Development Divis
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Chen Daniel
United Microelectronics Corporation (umc) Central R&d Division
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CHEN T.
United Microelectronics Corp., Specialty Technology Department, Technology & Process Development Div
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CHIEN S.
United Microelectronics Corp., Specialty Technology Department, Technology & Process Development Div
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SUN S.
United Microelectronics Corp., Specialty Technology Department, Technology & Process Development Div
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Lin Tony
United Microelectronics Corp. Technology Development Division
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Kuo Chien-Li
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Shen Tzermin
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Jung Le-Tien
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Shiau Wei-Tsun
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Yu Lorenzo
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Lin Tony
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Gong Yoyi
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Tseng Jung-Tsung
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Gong Yoyi
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Tseng Jung-Tsung
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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Chen Daniel
United Microelectronics Corporation (UMC), Central R&D Division, No. 3, Li-Hsin Rd. 2, Science-Based Industrial Park, Hsin-chu city, Taiwan 30007, ROC
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