A Low Thermal Budget High Performance 0.25-0.18 μm Merged Logic Device and Dynamic Random Access Memory Application

概要

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Merged dynamic random access memory(DRAM)with logic technology has been widely investigated because of to its high on-chip memory bandwidth, low power consumption, customized memory size, and small footprint advantages. A low thermal budget 0.25-0.18 μm embedded DRAM technology has been developed to merge a high-performance logic device and high-density DRAM on the same chip. In this newly developed technology, shallow trench isolation, a triple well, TiSi_x polycide, titanium salicide, a self-aligned contact poly-via and a low thermal budget oxide-nitride-oxide(ONO)as well as Ta_2O_5 capacitor dielectircs used for 1 Gbit DRAM design, are being applied. A 32 Mbit synchronous DRAM macro was designed based on this technology and is proposed offered as a drop-in module for embedded DRAM applications.
社団法人応用物理学会の論文
2000-04-30