The Impact for Gate Oxide Scaling (32Å-12Å) and Power Supply for Sub-0.1μm CMOSFETs
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概要
- 論文の詳細を見る
- 2000-08-28
著者
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Chen J.
United Microelectronics Corp. Logic Technology Department Technology & Process Development Divis
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LIOU F.
United Microelectronics Corp., Specialty Technology Department, Technology & Process Development Div
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HUANG C.
United Microelectronics Corp. (UMC), CRD Logic Division
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YEH W.K.
United Microelectronics Corp., Logic Technology Department, Technology & Process Development Divisio
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LIN C.
United Microelectronics Corp., Logic Technology Department, Technology & Process Development Divisio
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CHENG S.
United Microelectronics Corp., Logic Technology Department, Technology & Process Development Divisio
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SHIH H.
United Microelectronics Corp., Logic Technology Department, Technology & Process Development Divisio
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Yeh W.k.
United Microelectronics Corp. Logic Technology Department Technology & Process Development Divis
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Liou F.
United Microelectronics Corp. Logic Technology Department Technology & Process Development Divis
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Lin C.
United Microelectronics Corp. Logic Technology Department Technology & Process Development Divis
関連論文
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- 56% pMOSFETs Drive Current Enhancement from Optimized Compressive Contact Etching Stop Layer (CESL) for 45nm Node CMOS
- The Impact for Gate Oxide Scaling (32Å-12Å) and Power Supply for Sub-0.1μm CMOSFETs
- Optimization of Active Geometry Configuration and Shallow Trench Isolation (STI) Stress for Advanced CMOS Devices