Silicon Selective Epitaxial Growth and Electrical Properties of Epi/Sidewall Interfaces

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概要

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• Facet formation and stacking fault generation in silicon selective epitaxial growth are studied. On selective epilayer surfaces, a {311} facet and a {111} microfacet are formed on a {100} and a {111} substrate, respectively. In selective epilayers, stacking faults are observed adjacent to the sidewall Facet-free and stacking-fault-free selective epilayers are obtained using the $\langle 100\rangle$-orinted sidewall at low growth temperatures. These results are explained by an epitaxial growth model at hollow bridge sites. Electrical properties of the interfaces between the selective epilayer and the sidewall are also studied. The $\langle 100\rangle$-oriented SiO2 sidewall has better electrical characteristics than other sidewall orientations and sidewall materials.

• INSTITUTE OF PURE AND APPLIED PHYSICSの論文
• 1989-05-20

著者

• Kasai Naoki

  Microelectronics Research Laboratories Nec Corporation

• KITAJIMA Hiroshi

  Fundamental Research Laboratories

• Endo Nobuhiro

  Microelectronics Research Laboratories

• Ishitani Akihiko

  Fundamental Research Laboratories Nec Corporation

• Ishitani Akihiko

  Fundamental Research Laboratories, NEC Corporation, 1-1 Miyazaki 4-chome, Miyamae-ku, Kawasaki 213

• Kitajima Hiroshi

  Fundamental Research Laboratories, NEC Corporation, 1-1 Miyazaki 4-chome, Miyamae-ku, Kawasaki 213

• Kasai Naoki

  Microelectronics Research Laboratories, NEC Corporation, 1-1 Miyazaki 4-chome, Miyamae-ku, Kawasaki 213

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• Silicon Selective Epitaxial Growth and Electrical Properties of Epi/Sidewall Interfaces

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