Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization

スポンサーリンク

概要

• 論文の詳細を見る

• Pseudo Power Gating (Pseudo PG) is one of gate level power reduction methods for combinational circuits by stopping unnecessary input changes of gates. In Pseudo PG, an extra control signal might be added to a gate and other input changes of the gate are deactivated when the control signal takes the controlling value. To improve the power reduction capability, the paper newly introduces dual-stage Pseudo PG with advanced clustering algorithm where up to two extra control signals are added to a gate if effective. The advanced clustering algorithm selects the first control signal to be compatible with the second control signal based on the propagation of controlling condition via a path, with which candidates of controllable gates excluded by the maximum depth constraint can be controlled. Experimental results show that the proposed dual-stage Pseudo PG method has obtained 23.23% average power reduction with 5.28% delay penalty with respect to the original circuits, and has obtained 10.46% more power reduction with 2.75% delay penalty compared with respect to circuits applying the original single-stage Pseudo PG.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Kimura Shinji

  Graduate School Of Engineering Nagoya University

• KIMURA Shinji

  Graduate School of Information, Production and Systems, Waseda University

• JIN Yu

  Graduate School of Information, Production and Systems, Waseda University

• DU Zhe

  Graduate School of Information, Production and Systems, Waseda University

関連論文

• Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization (Special Section on VLSI Design and CAD Algorithms)
• Hardware Synthesis from C Programs with Estimation of Bit Length of Variables (Special Section on VLSI Design and CAD Algorithms)
• Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
• The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
• Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
• Fine-grained power gating based on the controlling value of logic gates (VLSI設計技術)
• Fine-grained power gating based on the controlling value of logic gates (システムLSI設計技術)
• Finite Input-Memory Automaton Based Checker Synthesis of System Verilog Assertions for FPGA Prototyping
• _
• Issue Mechanism for Embedded Simultaneous Multithreading Processor
• Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
• RAY-SPACE CODING USING SINUSOIDAL STRUCTURE IN CIRCULAR CAMERA ARRANGEMENT(International Workshop on Advanced Image Technology 2006)
• Characteristics of Hyaluronate-hydroxyethyl Acrylate Blend Gel and Release of Cationic Amphiphilic Solutes
• Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique(System Level Design,VLSI Design and CAD Algorithms)
• A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction(Test)(VLSI Design and CAD Algorithms)
• A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs(Test)(VLSI Design and CAD Algorithms)
• Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity
• Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification(Simulation and Verification,VLSI Design and CAD Algorithms)
• Structural Coverage of Traversed Transitions for Symbolic Model Checking
• Structural Coverage of Traversed Transitions for Symbolic Model Checking
• Structural Coverage of Traversed Transitions for Symbolic Model Checking
• Structural Coverage of Traversed Transitions for Symbolic Model Checking
• Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
• Checker circuit generation for System Verilog Assertions in prototyping verification (システムLSI設計技術)
• Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration
• Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
• Multi-Operand Adder Synthesis Targeting FPGAs
• On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating
• Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis
• An Exact Approach for GPC-Based Compressor Tree Synthesis
• Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization

もっと見る 閉じる

スポンサーリンク