On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating
スポンサーリンク
概要
- 論文の詳細を見る
In recent years, the demand for low-power design has remained undiminished. In this paper, a pseudo power gating (SPG) structure using a normal logic cell is proposed to extend the power gating to an ultrafine grained region at the gate level. In the proposed method, the controlling value of a logic element is used to control the switching activity of modules computing other inputs of the element. For each element, there exists a submodule controlled by an input to the element. Power reduction is maximized by controlling the order of the submodule selection. A basic algorithm and a switching activity first algorithm have been developed to optimize the power. In this application, a steady maximum depth constraint is added to prevent the depth increase caused by the insertion of the control signal. In this work, various factors affecting the power consumption of library level circuits with the SPG are determined. In such factors, the occurrence of glitches increases the power consumption and a method to reduce the occurrence of glitches is proposed by considering the parity of inverters. The proposed SPG method was evaluated through the simulation of the netlist extracted from the layout using the VDEC Rohm 0.18µm process. Experiments on ISCAS'85 benchmarks show that the reduction in total power consumption achieved is 13% on average with a 2.5% circuit delay degradation. Finally, the effectiveness of the proposed method under different primary input statistics is considered.
著者
-
Kimura Shinji
Graduate School Of Engineering Nagoya University
-
JIN Yu
Graduate School of Information, Production and Systems, Waseda University
関連論文
- Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization (Special Section on VLSI Design and CAD Algorithms)
- Hardware Synthesis from C Programs with Estimation of Bit Length of Variables (Special Section on VLSI Design and CAD Algorithms)
- Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
- Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
- Fine-grained power gating based on the controlling value of logic gates (VLSI設計技術)
- Fine-grained power gating based on the controlling value of logic gates (システムLSI設計技術)
- Finite Input-Memory Automaton Based Checker Synthesis of System Verilog Assertions for FPGA Prototyping
- _
- Issue Mechanism for Embedded Simultaneous Multithreading Processor
- Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
- RAY-SPACE CODING USING SINUSOIDAL STRUCTURE IN CIRCULAR CAMERA ARRANGEMENT(International Workshop on Advanced Image Technology 2006)
- Characteristics of Hyaluronate-hydroxyethyl Acrylate Blend Gel and Release of Cationic Amphiphilic Solutes
- Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique(System Level Design,VLSI Design and CAD Algorithms)
- A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction(Test)(VLSI Design and CAD Algorithms)
- A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs(Test)(VLSI Design and CAD Algorithms)
- Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity
- Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification(Simulation and Verification,VLSI Design and CAD Algorithms)
- Structural Coverage of Traversed Transitions for Symbolic Model Checking
- Structural Coverage of Traversed Transitions for Symbolic Model Checking
- Structural Coverage of Traversed Transitions for Symbolic Model Checking
- Structural Coverage of Traversed Transitions for Symbolic Model Checking
- Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
- Checker circuit generation for System Verilog Assertions in prototyping verification (システムLSI設計技術)
- Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration
- Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
- Multi-Operand Adder Synthesis Targeting FPGAs
- On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating
- Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis
- An Exact Approach for GPC-Based Compressor Tree Synthesis
- Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization