Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating

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概要

• 論文の詳細を見る

• Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.

• （社）電子情報通信学会の論文
• 2010-12-01

著者

• Kimura Shinji

  Graduate School Of Information Production And Systems Waseda University

• HORIYAMA Takashi

  Graduate School of Science and Engineering, Saitama University

• Horiyama Takashi

  Graduate School Of Engineering Kyoto University

• Man Xin

  Graduate School Of Information Production And Systems Waseda University

• Kimura Shinji

  Graduate School Of Engineering Nagoya University

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