Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis
スポンサーリンク
概要
- 論文の詳細を見る
Nonvolatile flip-flop enables leakage power reduction in logic circuits and quick return from standby mode. However, it has limited write endurance, and its power consumption for writing is larger than that of conventional D flip-flop (DFF). For this reason, it is important to reduce the number of write operations. The write operations can be reduced by stopping the clock signal to synchronous flip-flops because write operations are executed only when the clock is applied to the flip-flops. In such clock gating, a method using Exclusive OR (XOR) of the current value and the new value as the control signal is well known. The XOR based method is effective, but there are several cases where the write operations can be reduced even if the current value and the new value are different. The paper proposes a method to detect such unnecessary write operations based on state transition analysis, and proposes a write control method to save power consumption of nonvolatile flip-flops. In the method, redundant bits are detected to reduce the number of write operations. If the next state and the outputs do not depend on some current bit, the bit is redundant and not necessary to write. The method is based on Binary Decision Diagram (BDD) calculation. We construct write control circuits to stop the clock signal by converting BDDs representing a set of states where write operations are unnecessary. Proposed method can be combined with the XOR based method and reduce the total write operations. We apply combined method to some benchmark circuits and estimate the power consumption with Synopsys NanoSim. On average, 15.0% power consumption can be reduced compared with only the XOR based method.
著者
-
Kimura Shinji
Graduate School Of Engineering Nagoya University
-
Nakamura Yuichi
Green Platform Research Laboratories, NEC Corp.
-
OKADA Naoya
Graduate School of Information, Production and Systems, Waseda University
関連論文
- Exact Minimization of Free BDDs and Its Application to Pass-Transistor Logic Optimization (Special Section on VLSI Design and CAD Algorithms)
- Hardware Synthesis from C Programs with Estimation of Bit Length of Variables (Special Section on VLSI Design and CAD Algorithms)
- Selective Low-Care Coding : A Means for Test Data Compression in Circuits with Multiple Scan Chains(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
- Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
- Fine-grained power gating based on the controlling value of logic gates (VLSI設計技術)
- Fine-grained power gating based on the controlling value of logic gates (システムLSI設計技術)
- Finite Input-Memory Automaton Based Checker Synthesis of System Verilog Assertions for FPGA Prototyping
- _
- Issue Mechanism for Embedded Simultaneous Multithreading Processor
- Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis(Logic and High Synthesis)(VLSI Design and CAD Algorithms)
- RAY-SPACE CODING USING SINUSOIDAL STRUCTURE IN CIRCULAR CAMERA ARRANGEMENT(International Workshop on Advanced Image Technology 2006)
- Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique(System Level Design,VLSI Design and CAD Algorithms)
- A Selective Scan Chain Reconfiguration through Run-Length Coding for Test Data Compression and Scan Power Reduction(Test)(VLSI Design and CAD Algorithms)
- A Hybrid Dictionary Test Data Compression for Multiscan-Based Designs(Test)(VLSI Design and CAD Algorithms)
- Optimizing Controlling-Value-Based Power Gating with Gate Count and Switching Activity
- Coverage Estimation Using Transition Perturbation for Symbolic Model Checking in Hardware Verification(Simulation and Verification,VLSI Design and CAD Algorithms)
- Structural Coverage of Traversed Transitions for Symbolic Model Checking
- Structural Coverage of Traversed Transitions for Symbolic Model Checking
- Structural Coverage of Traversed Transitions for Symbolic Model Checking
- Structural Coverage of Traversed Transitions for Symbolic Model Checking
- Power Optimization of Sequential Circuits Using Switching Activity Based Clock Gating
- Checker circuit generation for System Verilog Assertions in prototyping verification (システムLSI設計技術)
- Efficient Hybrid Grid Synthesis Method Based on Genetic Algorithm for Power/Ground Network Optimization with Dynamic Signal Consideration
- Automatic Multi-Stage Clock Gating Optimization Using ILP Formulation
- Multi-Operand Adder Synthesis Targeting FPGAs
- On Gate Level Power Optimization of Combinational Circuits Using Pseudo Power Gating
- A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes
- A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes
- Write Control Method for Nonvolatile Flip-Flops Based on State Transition Analysis
- An Exact Approach for GPC-Based Compressor Tree Synthesis
- Dual-Stage Pseudo Power Gating with Advanced Clustering Algorithm for Gate Level Power Optimization