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概要
- 論文の詳細を見る
Reduction of verification period is the crucial problem in the recent LSI designs, and prototyping/emulation technologies are used for the reduction. Assertion-Based Verification (ABV) has been paid attention to check design errors at run time in simulation, and it has become an important to combine ABV with the prototyping. In the manuscript, we discuss about a generation method of checker circuit for System Verilog Assertions (SVA's). SVA is one of standard method to describe assertions in ABV. In the checker circuit generation, we focus on the hardware cost reduction.
- 2008-05-01
著者
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Kimura Shinji
Graduate School Of Engineering Nagoya University
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Wang Mengru
Graduate School Of Information Production And Systems Waseda University
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木村 晋二
Graduate School of Information Production and Systems, Waseda University
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