A Design Framework for Reconfigurable IPs with VLSI CADs

スポンサーリンク

概要

• 論文の詳細を見る

• The conventional FPGA design CAD flows evaluate FPGA architecture by implementing benchmarks through the following steps:synthesis, technology mapping, clustering and placement and routing (P&R). The area and timing performance reports are derived from the P&R tool. The accuracy of the result is low but proved enough to evaluate architectures fairly. However, for a complete FPGA IP design, the architecture should be evaluated with standard cells by the full back-end design flow. We proposed a new FPGA routing tool, namely EasyRouter. By using simple HDL templates, the EasyRouter can automatically generate entire chip HDL codes and the configuration bitstream according to architecture definition and routing result. With these files, the FPGA IP can be evaluated with commercial VLSI CADs in high accuracy and reliability.

• 一般社団法人電子情報通信学会の論文
• 2012-09-11

著者

• Iida Masahiro

  Graduate School Of Science And Technology Kumamoto University

• Amagasaki Motoki

  Graduate School Of Science And Technology Kumamoto University

• Sueyoshi Toshinori

  Graduate School Of Science And Technology Kumamoto University

• Inoue Kazuki

  Graduate School Of Science And Technology Kumamoto University

• Zhao Qian

  Graduate School Of Science And Technology Kumamoto University

関連論文

• An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device
• Configurable and Reconfigurable Computing for Digital Signal Processing(Special Section on the Trend of Digital Signal Processing and Its Future Direction)
• A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices(Reconfigurable Systems)
• A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
• An Easily Testable Routing Architecture and Prototype Chip
• Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration
• COGRE : A Novel Compact Logic Cell Architecture for Area Minimization
• FPGA Design Framework Combined with Commercial VLSI CAD
• Sensor Scheduling Algorithms for Extending Battery Life in a Sensor Node
• A Design Framework for Reconfigurable IPs with VLSI CADs

スポンサーリンク