A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices(<Special Section>Reconfigurable Systems)
スポンサーリンク
概要
- 論文の詳細を見る
High power consumption is a constraining factor for the growth of programmable logic devices. We propose two techniques in order to reduce power consumption. The first is a technique for creating contexts. This technique uses data-dependent circuits and wire sharing between contexts. The second is a technique for switching the contexts. In this paper, we evaluate the capability of the two techniques to reduce power consumption using a multi-context logic device. As a result, as compared with the original circuit, our multi-context circuits reduced the power consumption by 9.1% on an average and by a maximum of 19.0%. Furthermore, applying our resource sharing technique to these circuits, we achieved a reduction of 10.6% on an average and a maximum reduction of 18.8%.
- 社団法人電子情報通信学会の論文
- 2007-12-01
著者
-
Monji Hideaki
Graduate School Of Science And Technology Kumamoto University
-
Shinohara Hiroshi
Graduate School Of Science And Technology Kumamoto University
-
Iida Masahiro
Kumamoto Univ. Kumamoto Jpn
-
Iida Masahiro
Graduate School Of Science And Technology Kumamoto University
-
SUEYOSHI Toshinori
Graduate School of Science and Technology, Kumamoto University
-
Sueyoshi Toshinori
Kumamoto Univ. Kumamoto Jpn
-
Sueyoshi Toshinori
Graduate School Of Science And Technology Kumamoto University
関連論文
- An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device
- Configurable and Reconfigurable Computing for Digital Signal Processing(Special Section on the Trend of Digital Signal Processing and Its Future Direction)
- A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices(Reconfigurable Systems)
- Special Section on Reconfigurable Systems
- A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
- An Easily Testable Routing Architecture and Prototype Chip
- Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration
- COGRE : A Novel Compact Logic Cell Architecture for Area Minimization
- FPGA Design Framework Combined with Commercial VLSI CAD
- A Design Framework for Reconfigurable IPs with VLSI CADs