Configurable and Reconfigurable Computing for Digital Signal Processing(<特集>Special Section on the Trend of Digital Signal Processing and Its Future Direction)

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概要

• 論文の詳細を見る

• Recent DSP applications have many significant issues such as higher system performance, lower power consumption, higher design flexibility, faster time-to-market, and so on. Neither a conventional ASIC nor a conventional DSP can necessarily satisfy all the requirements at once nowadays. Therefore, an alternate for DSP applications will be needed to complement the drawbacks of ASICs and DSPs. This paper introduces a new computing paradigm called configurable computing or reconfigurable computing, which has more potential in terms of performance and flexibility. Conventional silicon platforms will not satisfy the conflicting demands of standard products and customization. However, silicon platforms such as FPGAs for configurable or reconfigurable computing are standardized in manufacturing but customized in application. This paper also presents a brief survey of the existing silicon platforms that support configuration or reconfiguration in the application domain of digital signal processing such as image processing, communication processing, audio and speech processing. Finally, we show some promising reconfigurable architectures for the digital signal processing and discuss the future of reconfigurable computing.

• 社団法人電子情報通信学会の論文
• 2002-03-01

著者

• Iida Masahiro

  Graduate School Of Science And Technology Kumamoto University

• Iida M

  Graduate School Of Science And Technology Kumamoto University

• SUEYOSHI Toshinori

  Department of Computer Science, Faculty of Engineering, Kumamoto University

• Sueyoshi Toshinori

  Department Of Computer Science Faculty Of Engineering Kumamoto University

• Sueyoshi Toshinori

  Department Of Artificial Intelligence Kyushu Institute Of Technology

関連論文

• An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device
• Configurable and Reconfigurable Computing for Digital Signal Processing(Special Section on the Trend of Digital Signal Processing and Its Future Direction)
• A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable Logic Devices(Reconfigurable Systems)
• A High-Performance Cluster Computing Environment Based on Hybrid Shared Memory/Message Passing Model (Special Issue on Parallel and Distributed Supercomputing)
• A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells
• An Easily Testable Routing Architecture and Prototype Chip
• Fault-Injection Analysis to Estimate SEU Failure in Time by Using Frame-Based Partial Reconfiguration
• COGRE : A Novel Compact Logic Cell Architecture for Area Minimization
• FPGA Design Framework Combined with Commercial VLSI CAD
• A Design Framework for Reconfigurable IPs with VLSI CADs

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