Sensor Scheduling Algorithms for Extending Battery Life in a Sensor Node

スポンサーリンク

概要

• 論文の詳細を見る

• Wireless sensor nodes are becoming more and more common in various settings and require a long battery life for better maintainability. Since most sensor nodes are powered by batteries, energy efficiency is a critical problem. In an experiment, we observed that when peak power consumption is high, battery voltage drops quickly, and the sensor stops working even though some useful charge remains in the battery. We propose three off-line algorithms that extend battery life by scheduling sensors' execution time that is able to reduce peak power consumption as much as possible under a deadline constraint. We also developed a simulator to evaluate the effectiveness of these algorithms. The simulation results showed that one of the three algorithms dramatically can extend battery life approximately three time as long as in simultaneous sensor activation.

著者

• NAKAMOTO Yukikazu

  Graduate School of Applied Informatics, University of Hyogo

• Nakamoto Yukikazu

  Graduate School Of Applied Informatics University Of Hyogo

• Zhao Qian

  Graduate School Of Science And Technology Kumamoto University

• IWATA Makoto

  System Technologies Laboratories, NEC System Technologies Limited

• YAMADA Shimpei

  Graduate School of Applied Informatics, University of Hyogo

• YAMAMURA Koutaro

  System Technologies Laboratories, NEC System Technologies Limited

• KAI Masayoshi

  System Technologies Laboratories, NEC System Technologies Limited

関連論文

• Extending a Role Graph for Role-Based Access Control
• An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device
• Extending a Role Graph for Role-Based Access Control
• Adaptive Fair Resource Allocation for Energy and QoS Trade-Off Management
• COGRE : A Novel Compact Logic Cell Architecture for Area Minimization
• FPGA Design Framework Combined with Commercial VLSI CAD
• Sensor Scheduling Algorithms for Extending Battery Life in a Sensor Node
• A Design Framework for Reconfigurable IPs with VLSI CADs

スポンサーリンク