グループ署名回路のアーキテクチャ最適化

概要

論文の詳細を見る
Group signature scheme is one of the most active research area in recent cryptographic algorithms/applications. Typical signature algorithm is a combination of dozens of elliptic curve (EC), modular, integer and hash arithmetic operations on data whose bit width exceeds 1,000 bits. A full-H/W IP core is desired for the use of the group signature in SoCs in slow-clock mobile devices. In order to construct a high performance and configurable group signature IP, connecting multiple modular/EC arithmetic units (sub-IPs) and a simple controller not by a wide-band bus but by a narrow-band bus is appropriate. While conventional behavioral synthesis from C-language was used, the development of an additional behavioral synthesizer for parallel scheduling of sub-IP level (C function-library level) operations was necessary. We explored an optimum H/W architecture for a typical group signature algorithm and found that at most 5 modular sub-IPs is enough. Practical H/W speed of less than 0.1 seconds at 100MHz on a 130nm standard cell ASIC library was achieved.
社団法人電子情報通信学会の論文
2008-07-17