Stress in Inter-level Dielectric Oxides on Integrated SBT-based Ferroelectric Memories

概要

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Effects of thermal stress in interlayer dielectrics on the electrical properties of ferroelectric SBT-based capacitor have been investigated. Tetraethylorthosilicate (TEOS) undoped silicon oxide (USG) or/and tetraethylorthosilicate-O_3 (TEOS-O_3) borophosphosilicate glass (BPSG). The electrical properties were measured in the integrated capacitors covered with the dielectrics, after reactive ion etching for contact holes followed by recovery anneal at 700℃ and then Al metallization. The capacitors covered with the single layer of USG show electrically short failure in especially array of small-sized capacitor with a storage node less than 10×10μm^2. Improvement in the electrical properties was achieved through the stress control in dielectric layers using double layers consisting of TEOS-based USG and TEOS-O_3-based BPSG. The stress optimization by means of thickness changes in the dielectric layers results in high enough remanent polarization (>15 μC/cm^2) and low leakage current (<8×10^<-7> A/cm^2) measured at 3V.
社団法人電子情報通信学会の論文
1999-07-23