A Digital Neural Network Coprocessor with a Dynamically Reconfigurable Pipeline Architecture (Special Issue on New Architecture LSIs)
スポンサーリンク
概要
- 論文の詳細を見る
We have developed a digital coprocessor with a dynamically reconfigurable pipeline architecture specified for a layered neural network which executes on-chip learning. The coprocessor attains a learning speed of 18 MCUPS that is approximately twenty times that of the conventional DSP. This coprocessor obtains expansibility in the calculation through a larger multi-layer network by means of a network decomposition and a distributed processing approach.
- 社団法人電子情報通信学会の論文
- 1993-07-25
著者
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Inoue Atsuo
Electronics Research Laboratory Matsushita Electronics Corporation
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Inoue A
Mitsubishi Electric Corp. Itami‐shi Jpn
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OTSUKI Tatsuo
Electronics Research Laboratory, Matsushita Electronics Corporation
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Katsu Shin-ichi
Electronics Research Laboratory, Matsushita Electronics Corporation
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Morishita Takayuki
Electronics Research Laboratory, Matsushita Electronics Corporation
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Tamura Youichi
Electronics Research Laboratory, Matsushita Electronics Corporation
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Satonaka Takami
Electronics Research Laboratory, Matsushita Electronics Corporation
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Otsuki T
Panasonic Technol. Inc. Co Usa
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Katsu Shin-ichi
Electronics Research Laboratory Matsushita Electronics Corporation
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Tamura Youichi
Electronics Research Laboratory Matsushita Electronics Corporation
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Satonaka Takami
Electronics Research Laboratory Matsushita Electronics Corporation
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Otsuki Tatsuo
Electronics Research Laboratory Matsushita Electronics Corporation
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Morishita Takayuki
Electronics Research Laboratory Matsushita Electronics Corporation:faculty Of Computer Science And S
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Morishita Takayuki
Department Of Electrical And Electronic Engineering Faculty Of Engineering Okayama University
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Morishita Takayuki
Faculty Of Computer Science And System Engineering Okayama Prefectural University
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Inoue A
Microwave Device Development Department Mitsubishi Electric Corporation
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Tamura Y
Kyoto Inst. Of Technol. Kyoto‐shi Jpn
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