Design of a Novel MOS V_T Extractor Circuit
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概要
- 論文の詳細を見る
This paper describes a novel input-free MOS V_T extractor circuit. The circuit consists of a bias voltage block and a novel V_T extractor block. The proposed V_T extractor block has the advantages of the ground-referenced output, low influences of the nonideality, few numbers of transistors and no influence of the PMOS process. The PSpice simulations show the supply voltage range and the bias voltage range of the proposed circuit are wider than those of Johnson's on Wang's.
- 社団法人電子情報通信学会の論文
- 1995-09-25
著者
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Tanno Koichi
Faculty Of Engineering Miyazaki University
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Ishizuka Okihiko
Faculty Of Engineering Miyazaki University
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Tang Zhen
Faculty of Engineering, Miyazaki University
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Tang Zhen
Faculty Of Engineering Miyazaki University
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