A 1-V, 1-V_<p-p> Input Range, Four-Quadrant Analog Multiplier Using Neuron-MOS Transistors

概要

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In this paper, a four-quadrant analog multiplier consisting of four neuron-MOS transistors and two load resistors is proposed. The proposed multiplier can be operated at only 1 V. Furthermore, the input range of the multiplier is equal to 100% of the supply voltage. The theoretical harmonic distortion caused by mobility degradation and device mismatchs is derived in detail. The performance of the proposed multiplier is characterized through HSPICE simulations with a standard 2.0μm CMOS process with a double-poly layer. Simulations of the proposed multiplier demonstrate that the linearity error of 0.77% and a total harmonic distortion of 0.62% are obtained with full-scale input conditions. The maximum power consumption and -3dB bandwidth are 9.5μW and 107 MHz, respectively. The active area of the proposed multiplier is 210μm×140μm.
社団法人電子情報通信学会の論文
1999-05-25