Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit(<Special Section>Nonlinear Theory and its Applications)
スポンサーリンク
概要
- 論文の詳細を見る
In this letter, we propose a sample and hold circuit (S/H circuit) with the clock boost technique and the input signal tracking technique. The proposed circuit block generates the clock with the amplitude of V_<DD>+υ_<in>, and the clock is used to control the MOS switch. By applying this circuit to a S/H circuit, we can deal with the rail-to-rail signal with maintaining low distortion. Furthermore, the hold error caused by the charge injection and the clock feedthrough can be also reduced by using the dummy switch. The Star-HSPICE simulation results are reported in this letter.
- 社団法人電子情報通信学会の論文
- 2005-10-01
著者
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TANAKA Hisashi
Department of Radiology, Osaka University, Graduate School of Medicine
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TANNO Koichi
Faculty of Engineering, Miyazaki University
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ISHIZUKA Okihiko
Faculty of Engineering, Miyazaki University
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Tanaka Hisashi
Department Of Radiology Graduate School Of Medicine Osaka University
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Tanno Koichi
Faculty Of Engineering University Of Miyazaki
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Tanno Koichi
Faculty Of Engineering Miyazaki University
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Ishizuka Okihiko
Faculty Of Engineering University Of Miyazaki
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Ishizuka Okihiko
Faculty Of Engineering Miyazaki University
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Sato Kiminobu
Faculty Of Engineering University Of Miyazaki
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Tanno Koichi
Dep. Of Electrical And Electronic Engineering Fac. Of Engineering Univ. Of Miyazaki
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Tanaka Hisashi
Faculty Of Engineering University Of Miyazaki
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Tanaka Hisashi
Department Of Diagnostic Radiology University Of Rochester Medical Center
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