A Fine Grain Cooled Logic Architecture for Low-Power Processors(Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
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概要
- 論文の詳細を見る
In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.
- 社団法人電子情報通信学会の論文
- 2001-03-01
著者
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NAKAMURA Tadao
Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku Un
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MATSUBARA HIROYUKI
Department of Urology, Aichi Medical University School of Medicine
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WATANABE Takahiro
Department of Civil Engineering, The University of Tokyo
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Watanabe T
School Of Administration And Informatics University Of Shizuoka
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Matsubara Hiroyuki
Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku Univ
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Matsubara Hiroyuki
Department Of Physics Faculty Of Science Shizuoka University.
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Nakamura Toshio
Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku Univ
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Watanabe T
Department Of Computer Science And Systems Engineering Faculty Of Engineering Yamaguchi University
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Nakamura Tadao
Department Of Computer And Mathematical Sciences Graduate School Of Information Sciences Tohoku Univ
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Watanabe Takahiro
Department Of Civil Engineering The University Of Tokyo
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