An Effective Routing Methodology for Gb/s LSIs Using Deep-Submicron Technology
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概要
- 論文の詳細を見る
This paper presents a routing methodology and a routing algorithm used in designing Gb/s LSIs with deep-submicron technology. A routing method for controlling wire width and spacing is adopted for net groups classified according to wire length and maximum-allowable-delay constraints. A high-performance router using this method has been developed and can handle variable wire widths, variable spacing, wire shape control, and low-delay routing. For multiterminal net routing, a modification of variable-cost maze routing(GVMR)is effective for reducing wire capacitance(net length)and decreasing net delay. The methodology described here has been used to design an ATM-switch LSI using 0.25-μm CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s(2.5 Gbps/pin)and an internal clock frequency of 312 MHz.
- 社団法人電子情報通信学会の論文
- 1998-04-25
著者
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Ohtomo Y
Ntt System Electronics Lab. Atsugi‐shi Jpn
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Ohtomo Yusuke
Ntt System Electronics Laboratories
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Ohtomo Yusuke
The Authors Are With The Ntt System Electronics Laboratories
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Watanabe T
School Of Administration And Informatics University Of Shizuoka
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WATANABE Takumi
The authors are with the NTT Integrated Information and Energy Systems Laboratories
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YAMAKOSHI Kimihiro
The authors are with the NTT System Electronics Laboratories
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TAKEI Yuichiro
The authors are with the NTT Integrated Information and Energy Systems Laboratories
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Takei Y
Department Of Electrical Engineering Nagaoka University Of Technology
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Yamakoshi K
Ntt Corp. Musashino‐shi Jpn
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