A Global Router for Analog Function Blocks Based on the Branch-and-Bound Algorithm
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概要
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The main aim of device-level global routing is to obtain high-performance detailed routing under various layout constraints. This paper deals with global routing for analog function blocks. For analog LSIs, especially for those operating at high frequency, various layout constraints are specified prior to routing. Those constraints must be completely satisfied to achieve the required circuit performance. However, they are sometimes too hard to be solved by any heuristic method even if a problem is small in size. Thus, we propose a method based on the branch-and-bound algorithm, which can generate all possible solutions to find the best one. Unfortunately, the method tends to take a large amount of processing time. In order to defeat the drawbacks by accelerating the process, constraints are classified into two groups: constraints on single nets and constraints between two nets. Therefore our method consists of two parts: in the first part only constraints on single nets are processed and in the second part only constraints between two nets are processed. The method is efficient because many possible routes that violate layout constraints are rejected immediately in each part. This makes it possible to construct a smaller search tree and to reduce processing time. Additionally this idea, all nets processed in the second phase are sorted in the proper order to reduce the number of edges in the search tree. This saves much processing time, too. Experimental results show that our method can find a good global route for hard layout constraints in practical processing time, and also show that it is superior to the well-known simulated annealing method both in quality of solutions and in processing time.
- 社団法人電子情報通信学会の論文
- 1995-03-25
著者
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WATANABE Takahiro
Department of Civil Engineering, The University of Tokyo
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Watanabe T
School Of Administration And Informatics University Of Shizuoka
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Tsubota Tadanao
Semiconductor Systems Engineering Center, TOSHIBA CORPORATION
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Kawakita Masahiro
Semiconductor Systems Engineering Center, TOSHIBA CORPORATION
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Kawakita M
Osaka Univ. Suita‐shi Jpn
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Kawakita Masahiro
Semiconductor Company Toshiba Corp.
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Tsubota Tadanao
Semiconductor Systems Engineering Center Toshiba Corporation
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Watanabe Takahiro
Department Of Civil Engineering The University Of Tokyo
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Watanabe Takahiro
Department Of Computer Science And Systems Engineering Yamaguchi University
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