Ultra-Low Energy Ion Implant Profile Prediction for sub 0.1μm Technologies

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概要

• 論文の詳細を見る

• In this paper, we present the phenomenological local damage accumulation model and results of highly efficient molecular dynamics simulation. Proposed local damage accumulation model is composed by deposited energy, history of recoil event and heat conductance in a cell, and also considers effects of self-relaxation and self-recombination. The results of MDRANGE with local damage accumulation model agree with the experimental results and results of other simulation. We also simulated various doses and various ultra-low energies boron and arsenic ion implantation and dopant distribution for sub 0.1 μm technologies in real space. We obtained dopant profiles by real Ton number corresponding to dose on 0.1 μm × 0.1μm silicon surface in the <100> channeling direction. In the cases of both B and As, as ion dose and implant energy increase, dopant profiles are much affected by locally accumulated damage. Especially, dopant profiles are much influenced by locally accumulated damage at doses above 10^<14>/cm^2 regardless of implant energy.

• 社団法人電子情報通信学会の論文
• 1999-07-22

著者

• Kwon Oh-kyong

  Department Of Electrical Engineering Hanyang University

• Lee Young-ghik

  Semiconductor Process And Device Laboratory Dept. Of Electronic Engineering Chung-ang University

• Kwon O‐k

  Division Of Electrical And Computer Engineering Hanyang University

• Kwon Oh-keun

  Semiconductor Process And Device Laboratory Dept. Of Electronic Engineering Chung-ang University

• Kang Jeong-won

  Semiconductor Process And Device Laboratory Dept. Of Electronic Engineering Chung-ang University

• Hwang H‐j

  Chung‐ang Univ. Seoul Kor

• Lee Young-chul

  Pg.1 R&d Division Lg Semicon Co. Ltd.

• Choi J‐h

  Semiconductor Process And Device Laboratory Dept. Of Electronic Engineering Chung-ang University

• Choi Jea-hoon

  Semiconductor Process And Device Laboratory Dept. Of Electronic Engineering Chung-ang University

• Byun Ki-Ryang

  Semiconductor Process and Device Lab,, Dept. of Electronic Engineering, Chung-Ang Univ.

• Hwang Ho-Jung

  Semiconductor Process and Device Lab,, Dept. of Electronic Engineering, Chung-Ang Univ.

• Byun Ki-ryang

  Semiconductor Process And Device Laboratory Dept. Of Electronic Engineering Chung-ang University

• Kang Jeung-Won

  Semiconductor Process and Device Laboratory, Dept. of Electronic Engineering, Chung-Ang University

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