A Fast Delay Locking Circuit with Duty-Preservation
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概要
- 論文の詳細を見る
A two-clock-cycle locking and duty-preserving digital delay line is presented.The proposed delay line has a new matching detection circuit which can decide the tapping position within the detecting resolution range of 0.3ns.The proposed delay line can be used for duty preserved internal clock generation of double data rate DRAMs.SPICE simulation results show that the proposed delay line has good locking characteristics at the frequency range of 50MHz-250MHz using 0.35um CMOS process parameters.
- 社団法人電子情報通信学会の論文
- 1998-07-23
著者
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Kwon Oh-kyong
Department Of Electrical Engineering Hanyang University
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Kwon Oh-kyong
Department Of Electoronic Engineering Hanyang University
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Koh Yun-Hak
Department of Electronic Engineering, Hanyang University
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Koh Yun-hak
Department Of Electoronic Engineering Hanyang University
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