Design Philosophy of a Data-Driven Processor: Q-p
スポンサーリンク
概要
- 論文の詳細を見る
A bread-board prototype of a VLSI-oriented data-driven Processor or Q-P (Queue-prototype), which can handle history-sensitive processes under consistency constraints, has been developed jointly by Osaka University and four VLSI manufacturers: Sharp Corporation, Matsushita Electric, Sanyo Electric and Mitsubishi Electric. Since the Q-p is specifically designed to be a one-chip functional element that is easily programmable to form various dedicated processing functions, particular design considerations were taken to realize high flow-rate data-stream processing capabilities. This paper first introduces major objectives of the Q-p development project and then presents the Q-p's basic language structure to demonstrate advantages of diagrammatical representation of programs. After that, this paper reports an execution control based on the data-driven scheme incorporating history-sensitivity that gives rise to a unique "flow-thru processing" concept in which all processing, data-transfer and storage functions are carried out highly-parallel by a packetized data-flow through the elastic pipeline processing stages with completely distributed controls. This paper also reports the hardware structure of the emulated Q-p which allows us to fully utilize the available devices on a VLSI chip by means of a self-timed elastic pipeline scheme.
- 一般社団法人情報処理学会の論文
- 1988-03-10
著者
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NISHIKAWA Hiroaki
Department of Cardiology, Fukuoka University Hospital
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Nishikawa Hiroaki
Department Of Cardiology Faculty Of Medicine Fukuoka University
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Nishikawa Hiroaki
School Of Biology-oriented Science And Technology Kinki University
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Komori Shinji
兵庫医科大学先端医学研究所
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NISHIKAWA Hiroaki
the School of Biology-Oriented Science and Technology, Kinki University
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Asano Hajime
Corporate Engineering Division Systems Research Laboratory Matsushita Electric Ind. Co. Ltd.
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Nishikawa H
Osaka Univ. Osaka Jpn
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Nishikawa Hiroaki
College Of Medical Technology & Nursing University Of Tsukuba
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TERADA HIROAKI
Department of Electronic Engineering, Faculty of Engineering Osaka University
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ASADA KATSUHIKO
Department of Electronic Engineering, Faculty of Engineering Osaka University
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OKAMOTO TOSHIYA
Integrated Circuit Group, VLSI Development Laboratory Sharp Corporation
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MIYATA SOUICHI
Integrated Circuit Group, VLSI Development Laboratory Sharp Corporation
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TOKURA TSUYOSHI
Corporate Engineering Division, Systems Research Laboratory Matsushita Electric Ind. Co., Ltd.
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SHIMIZU MASAHISA
Research Center, Sanyo Electric Co., Ltd.
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HARA SHUJI
Research Center, Sanyo Electric Co., Ltd.
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KOMORI SHINJI
Dedicated Microprocessor Group, LSI R & D Laboratory Mitsubishi Electric Corporation
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SHIMA KENJI
Industrial Electronics Department, Product Development Laboratory Mitsubishi Electric Corporation
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Kobayashi Shin-ichiro
Advanced Fertility Center Huchu Hospital
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Nishikawa H
The Institute Of Scientific And Industrial Research Osaka University
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Nishikawa Hiroaki
The Author Is With Institute Of Information Science And Electronics University Of Tsukuba
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Nishikawa H
School Of Biology-oriented Science And Technology Kinki University
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Hara Shuji
Research Center Sanyo Electric Co. Ltd.
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Shima K
Department Of Computers And Systems Engineering Tokyo Denki University
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Komori S
Mitsubishi Electric Corp. Itami‐shi Jpn
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Miyata Souichi
Integrated Circuit Group Vlsi Development Laboratory Sharp Corporation
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寺田 浩詔
大阪大学工学部
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Shimizu Masahisa
Research Center Sanyo Electric Co. Ltd.
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Asada Katsuhiko
Department Of Electronic Engineering Faculty Of Engineering Osaka University
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Okamoto T
Matsushita Electric Industrial Co. Ltd.
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Tokura Tsuyoshi
Corporate Engineering Division Systems Research Laboratory Matsushita Electric Ind. Co. Ltd.
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Shima Kenji
Industrial Electronics & Systems Lab. Mitsubishi Electric Corporation
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