Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System
スポンサーリンク
概要
- 論文の詳細を見る
This paper proposes approaches to perform HW/SW (Hardware/Software) partition and parallelization of computing-intensive tasks of the H.264 HiP (High Profile) decoding algorithm on an embedded coarse-grained reconfigurable multimedia system, called REMUS (REconfigurable MUltimedia System). Several techniques, such as MB (Macro-Block) based parallelization, unfixed sub-block operation etc., are utilized to speed up the decoding process, satisfying the requirements of real-time and high quality H.264 applications. Tests show that the execution performance of MC (Motion Compensation), deblocking, and IDCT-IQ(Inverse Discrete Cosine Transform-Inverse Quantization) on REMUS is improved by 60%, 73%, 88.5% in the typical case and 60%, 69%, 88.5% in the worst case, respectively compared with that on XPP PACT (a commercial reconfigurable processor). Compared with ASIC solutions, the performance of MC is improved by 70%, 74% in the typical and in the worst case, respectively, while those of Deblocking remain the same. As for IDCT_IQ, the performance is improved by 17% no matter in the typical or worst case. Relying on the proposed techniques, 1080p@30fps of H.264 HiP@ Level 4 decoding could be achieved on REMUSwhen utilizing a 200MHz working frequency.
- 2010-12-01
著者
-
Geng Tongsheng
Institute Of Microelectronics Tsinghua University
-
Yin Shouyi
Institute Of Microelectronics Tsinghua University
-
Liu Leibo
Institute Of Microelectronics Tsinghua University
-
Zhu Min
Institute Of Microelectronics Tsinghua University
-
Wei Shaojun
Institute Of Microelectronics Tsinghua University
関連論文
- Compiler Framework for Reconfigurable Computing Architecture
- A Cycle-Accurate Simulator for a Reconfigurable Multi-Media System
- Parallelization of Computing-Intensive Tasks of the H.264 High Profile Decoding Algorithm on a Reconfigurable Multimedia System
- CropNET : A Wireless Multimedia Sensor Network for Agricultural Monitoring
- Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications
- Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture
- Fast AdaBoost-Based Face Detection System on a Dynamically Coarse Grain Reconfigurable Architecture
- Hybrid Wired/Wireless On-Chip Network Design for Application-Specific SoC
- Multi-Battery Scheduling for Battery-Powered DVS Systems
- Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications
- Mapping Optimization of Affine Loop Nests for Reconfigurable Computing Architecture
- Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip
- Affine Transformations for Communication and Reconfiguration Optimization of Mapping Loop Nests on CGRAs
- Parallelization of Computing-Intensive Tasks of SIFT Algorithm on a Reconfigurable Architecture System
- An Inductive-Coupling Interconnected Application-Specific 3D NoC Design
- Battery-Aware Task Mapping for Coarse-Grained Reconfigurable Architecture
- Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features
- Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip
- Concurrent Detection and Recognition of Individual Object Based on Colour and p-SIFT Features