VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4 x 4 MIMO-OFDM Receiver
スポンサーリンク
概要
- 論文の詳細を見る
MIMO-OFDM performs signal detection on a subcarrier basis which requires high speed computation in MIMO detection due to its large computational cost. Conventional designs in a MIMO detector increase processing time in proportion to the number of subcarriers and have difficulty in real-time processing for large numbers of subcarriers. A complete pipeline MMSE MIMO detector presented in our previous work can provide high speed computation. However, it tends to be excessive in a circuit scale for small numbers of subcarriers. We propose a new scalable architecture to reduce circuit scale by adjusting the number of iterative operations according to various types of OFDM system. The proposed detector has reduced circuit area to about 1/2 to 1/7 in the previous design with providing acceptable latency time.
- Institute of Electronics, Information and Communication Engineersの論文
- 2011-01-01
著者
-
YOSHIZAWA Shingo
Graduate School of Information Science and Technology, Hokkaido University
-
IKEUCHI Hirokazu
Graduate School of Information Science and Technology, Hokkaido University
-
Yoshizawa Shingo
Graduate School Of Engineering Hokkaido University
-
Miyanaga Yoshikazu
Graduate School Of Information Science And Technology Hokkaido University
-
Ikeuchi Hirokazu
Graduate School Of Information Science And Technology Hokkaido University
-
Miyanaga Yoshikazu
Graduate School Of Engineering Hokkaido University
関連論文
- VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4×4 MIMO-OFDM Receiver
- A-20-12 Data Frame Format for OFDM System with Variable FFT Point of Data
- Robust Speech Spectra Restoration against Unspecific Noise Conditions for Pitch Detection
- A-20-9 A Study of Phase and Distance Histogram Compensation for OFDM Blind Modulation Detection in Adaptive OFDM Communication
- Performance evaluation of quasi-cyclic LDPC codes for IEEE802.11n based MIMO-OFDM systems (スマートインフォメディアシステム)
- Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator(VLSI Design Technology and CAD)
- VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 × 4 MIMO-OFDM Receiver
- A Flexible Architecture for Digital Signal Processing(VLSI System)
- Noise-Robust Speech Analysis Using Running Spectrum Filtering(Speech and Hearing)
- Cepstral Amplitude Range Normalization for Noise Robust Speech Recognition(Speech and Hearing)
- Acoustic Analysis of Vocal Tract Using Auto-Mesh Generation of Finite Element Modeling(Digital Signal Processing)
- High-Speed Finite Element Computation in 3-D Acoustical Analysis of Vocal Tract
- VLSI Implementation of a Scalable Pipeline MMSE MIMO Detector for a 4 x 4 MIMO-OFDM Receiver
- W-04 NEXUS-the Next Generation e-Learning System-and FPGA Hardware Design Platform(International Session)
- Performance and Complexity of MIMO Detectors for Advanced Wireless Communications Systems
- Connectivity Modeling Analysis in Flight-Path Based Aviation Ad Hoc Networks
- New Error Resilience Technique Using Adaptive FMO and Intra Refresh for H.264 Video Transmission
- Design of Area- and Power-Efficient Pipeline FFT Processors for 8x8 MIMO-OFDM Systems
- Development and Outdoor Evaluation of an Experimental Platform in an 80-MHz Bandwidth 2×2 MIMO-OFDM System in 5.2-GHz Band
- A Noise-Robust Continuous Speech Recognition System Using Block-Based Dynamic Range Adjustment
- A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions
- A Dynamically Reconfigurable FPGA-Based Pattern Matching Hardware for Subclasses of Regular Expressions
- A Low Power Tone Recognition for Automatic Tonal Speech Recognizer
- Low-Power Dynamic MIMO Detection for a 4×4 MIMO-OFDM Receiver
- A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing
- A Robust Speech Communication into Smart Info-Media System
- Efficiency Improvement in Dynamic Time Warping Algorithms for Isolated Word Recognition