VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 × 4 MIMO-OFDM Receiver
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概要
- 論文の詳細を見る
This paper presents a VLSI architecture of MMSE detection in a 4×4 MIMO-OFDM receiver. Packet-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassens algorithms of matrix inversion and multiplication. This circuit achieves realtime operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and shows a potential for providing a 2.6-Gbps transmission speed in a 160-MHz signal bandwidth.
- （社）電子情報通信学会の論文
- 2008-07-01
著者
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YOSHIZAWA Shingo
Graduate School of Information Science and Technology, Hokkaido University
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MIYANAGA Yoshikazu
Graduate School of Information Science and Technology, Hokkaido University
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Yoshizawa Shingo
Graduate School Of Information Science And Technology Hokkaido University
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Yoshizawa Shingo
Graduate School Of Engineering Hokkaido University
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Miyanaga Yoshikazu
Graduate School Of Information Science And Technology Hokkaido University
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YAMAUCHI Yasushi
Graduate School of Information Science and Technology, Hokkaido University
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Yamauchi Yasushi
Graduate School Of Information Science And Technology Hokkaido University
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Miyanaga Yoshikazu
Graduate School Of Engineering Hokkaido University
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