A VLSI Design of a Tomlinson-Harashima Precoder for MU-MIMO Systems Using Arrayed Pipelined Processing

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概要

• 論文の詳細を見る

• This paper presents a VLSI design of a Tomlinson-Harashima (TH) precoder for multi-user MIMO (MU-MIMO) systems. The TH precoder consists of LQ decomposition (LQD), interference cancellation (IC), and weight coefficient multiplication (WCM) units. The LQ decomposition unit is based on an application specific instruction-set processor (ASIP) architecture with floating-point arithmetic for high accuracy operations. In the IC and WCM units with fixed-point arithmetic, the proposed architecture uses an arrayed pipeline structure to shorten a circuit critical path delay. The implementation result shows that the proposed architecture reduces circuit area and power consumption by 11% and 15%, respectively.

• The Institute of Electronics, Information and Communication Engineersの論文

著者

• Hatakawa Yasuyuki

  Kddi R&d Lab. Inc. Fujimino‐shi Jpn

• Miyanaga Yoshikazu

  Graduate School Of Engineering Hokkaido University

• Matsumoto Tomoko

  Kddi R&d Laboratories Inc.

• YOSHIZAWA Shingo

  Department of Electrical and Electronic Engineering, Kitami Institute of Technology

• Konishi Satoshi

  Kddi R&d Lab. Inc.

• SHIMAZAKI Kosuke

  Graduate School of Information Science and Technology, Hokkaido University

• KONISHI Satoshi

  KDDI R&D Lab.

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