Width Scaling and Layout Variation Effects on Dual Damascene Copper Interconnects Electromigration

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概要

• 論文の詳細を見る
• 2005-09-13

著者

• Lin M.

  United Microelectronics Corp. Specialty Technology Department Technology & Process Development D

• Wang Tahui

  Department Of Electronic Engineering National Chiao Tung University

• CHANG K.

  United Microelectronics-Singapore Corp., Advanced Process Integration

• SU K.

  United Microelectronics Corp.

関連論文

• Simulation of Positive Oxide Trapped Charge Induced Leakage Current and Read-Disturb in Flash EEPROMs
• Stress Induced Subthreshold Current Hump in Short Gate-Length pMOSFET's with Shallow Trench Isolation
• Temperature Effect on Off-State Drain Leakage Current in a Hot-Carrier Stressed n-MOSFET
• A Comparative Study of Interface Trap Induced Drain Leakage Current in Various n-MOSFET Structures
• A Low Thermal-Budget High-Performanced 0.25-0.18um Merged Logic and DRAM
• Oxide Thickness Dependence of Hot Carrier Stress Induced Drain Leakage Current Degradation in Thin-Oxide n-MOSFET's
• Deuterium Effect on Stress-Induced Leakage Current
• A High Performance Embedded 60nm Gate Length CMOSFET with Novel Strained Silicon Process
• Floating Body Accelerated Oxide Breakdown Progression in Ultra-Thin Oxide SOI pMOSFETs
• Width Scaling and Layout Variation Effects on Dual Damascene Copper Interconnects Electromigration
• A Novel Soft-Program for a Narrow Erased State Vt Distribution, Read Disturbance Suppression and Over-Program Annihilation in Multilevel Cell Flash Memories
• Copper Interconnect Electromigration Behavior in Various Structures and Precise Bimodal Fitting

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