Impact of Negative-Bias Temperature Instability on the Lifetime of Single-Gate CMOS Structures with Ultrathin(4-6nm)Gate Oxides

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概要

• 論文の詳細を見る
• 1995-08-21

著者

• Shiono N

  Ntt Lsi Laboratories Nippon Telegraph And Telephone Corporation

• OGAWA Shigeo

  NTT LSI Laboratories

• Ogawa Shigeo

  Ntt Lsi Laboratories Nippon Telegraph And Telephone Corporation

• Shimaya M

  Ntt Telecommunications Energy Laboratories

• Shimaya Masakazu

  Ntt Lsi Laboratories

• SHIONO Noboru

  Reliability Center for Electronic Components of Japan (RCJ)

関連論文

• Evaluation of Hot-Hole Induced Interface Traps at the Tunneling SiO_2(3.5nm)-Si Interface by the Conductance Technique
• The Influence of Stud Bumping above the MOSFETs on Device Reliability(Special Section on Reliability Theory and Its Applications)
• Stress-Induced Device Degradation Due to Die-Attachment Process after Area Bump Formation
• Stress-Induced Device Degradation Due to Die-Attach Process after Area Bump Formation
• Impact of Negative-Bias Temperature Instability on the Lifetime of Single-Gate CMOS Structures with Ultrathin (4–6 nm) Gate Oxides
• Impact of Negative-Bias Temperature Instability on the Lifetime of Single-Gate CMOS Structures with Ultrathin(4-6nm)Gate Oxides
• Electron Trapping Inducedby High-Energy Ionizing Radiation in SiO_2
• An Analysis of and a Method of Enhancing the Intensity of OBIRCH Signal for Defects Observation in VLSI Metal Interconnections (Special Issue on LSI Failure Analysis)

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