The Influence of Stud Bumping above the MOSFETs on Device Reliability(Special Section on Reliability Theory and Its Applications)

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概要

• 論文の詳細を見る

• This paper presents the effect of stress on device degradation in metal-oxide-semiconductor field-effect transistors(MOSFETs)due to stud bumping. Stud bumping above the MOSFET region generates interface traps at the Si/SiO_2 interface and results in the degradation of transconductance in N-channel MOSFETs. The interface traps are apparently eliminated by both nitrogen and hydrogen annealing. However, the hot-carrier immunity after hydrogen annealing is one order of magnitude stronger than that after nitrogen annealing. This effect is explained by the termination of dangling bonds with hydrogen atoms.

• 社団法人電子情報通信学会の論文
• 2000-05-25

著者

• MACHIDA Katsuyuki

  NTT Telecommunications Energy Laboratories, NTT Corporation

• KYURAGI Hakaru

  NTT Telecommunications Energy Laboratories, NTT Corporation

• MACHIDA Katsuyuki

  NTT Advanced Technology Corporation

• Shimoyama Nobuhiro

  Ntt Lifestyle And Environmental Laboratories

• Kyuragi H

  Ntt Microsystem Integration Laboratories Ntt Corporation

• Akiya Hideo

  Ntt Telecommunications Energy Laboratories

• SHIMAYA Masakazu

  NTT Telecommunications Energy Laboratories

• Shimaya M

  Ntt Telecommunications Energy Laboratories

• Machida K

  Ntt Advanced Technology Corporation

• Machida Katsuyuki

  NTT Telecommunications Energy Laboratories, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0198, Japan

• Kyuragi Hakaru

  NTT Telecommunications Energy Laboratories, 3-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0198, Japan

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