A Novel LOCOS-Trench Combination Isolation Method for Maximum Chemical Mechanical Polishing(CMP) Process Window

スポンサーリンク

概要

論文の詳細を見る
1996-08-26

著者

関連論文

Electrical and Microstructural Analyses on the Au/Ni/Au/Ge/Pd Ohmic Contact to n-InGaAs and n-GaAs
Electrical and Microstructural Analyses on Pd/Ge-Based Ohmic Contact to n-InGaAs
Heterogeneous Particle Formation during Low Pressure Etching of Silicon Dioxide
Deposition Characteristics of (Ba, Sr)TiO_3 Thin Films by Liquid Source Metal-Organic Chemical Vapor Deposition at Low Substrate Temperatures
Variation of Electrical Conduction Phenomena of Pt/(Ba, Sr)TiO_3/Pt Capacitors by Different Top Electrode Formation Processes
A New, Low-Thermal-Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured Hydrogen Silsesquioxane in Device
A Novel and Low Thermal Budget Planarization Scheme for Pre-Metal Dielectric Using Electron-Beam Cured HSQ (Hydrogen Silsesquioxane) in STC (Stacked Capacitor) DRAM
Enhancement of Mask Selectivity in SiO_2 Etching with a Phase-Controlled Pulsed Inductively Coupled Plasma
Characteristics of a Stabilized Pulsed Plasma via Suppression of Side-Band Modes
Effect of SiO_2 Film Deposition on the Ferroelectric Properties of a Pt/Pb(Zr,Ti)O_3/Pt Capacitor
Preparation and Electrical Properties of SrTiO3 Thin Films Deposited by Liquid Source Metal-Organic Chemical Vapor Deposition (MOCVD)
Deposition and Electrical Characterization of Very Thin SrTiO_3 Films for Ultra Large Scale Integrated Dynamic Random Access Memory Application
Degradation and Recovery in the Ferroelectric Properties of Pt/Pb(Zr,Ti)O_3/Pt capacitor caused by SiO_2 Film Deposition
Degradation and Recovery in the Ferroelectric Properties of Pt/Pb(Zr,Ti)O_3/Pt capacitor caused by SiO_2 Film Deposition
Structural and Electrical Properties of Ba_Sr_TiO_3 Films on Ir and IrO_2 Electrodes
Preparation and Characterization of Iridium Oxide Thin Films Grown by DC Reactive Sputtering
A Novel T-Shaped Shallow Trench Isolation Technology
Improvement of Photo-Misalignment in Patterned Wafer Bonding Process for Silicon-on-Insulator Device
A Novel LOCOS-Trench Combination Isolation Method for Maximum Chemical Mechanical Polishing(CMP) Process Window
The Effect of Stress on Solid-Phase Epitaxial RegroWth in As^+ -Implanted Two-Dimensional Amorphized Si : Semiconductors
A Novel T-Shaped Shallow Trench Isolation Technology
Advanced 10 nm Width Silicon-on-Insulator Tri-Gate Transistors with NO Annealing of Gate Oxide Using Optimized Novel Silicon-on-Insulator Realization Technology

もっと見る

スポンサーリンク