Impact of Aggressively Shallow Source/Drain Extensions on Device Performance

概要

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We investigated by numerical simulations the effect of aggressive reduction of the source/drain extension (SDE) depth $X_{ j}$ on the performance of a metal–oxide–semiconductor field-effect transistor (MOSFET) of the 45-nm technology node. As an extreme case, the charge-transfer-doped SDE MOSFET (CTE-MOS), which has inversion-layer SDEs induced by surface charges, was considered. Assuming that the gate length $L_{\text{g}}$ fluctuation was $\pm 20$%, the substrate doping was set so that the off-state current was a specified value at $L_{\text{g}}=-20$%, and the resulting drive current $I_{\text{on}}$ at $L_{\text{g}}=+20$% was evaluated. When $X_{ j}$ was reduced from 9.5 to 2.0 nm under a fixed impurity density of $2\times 10^{20}$ cm-3, $I_{\text{on}}$ increased by ${\sim}27$% because the SDE resistance increase was compensated for by the reduction of the short-channel effects. CTE-MOS exhibited a still better performance: 1–1.3 times $I_{\text{on}}$ and 1.1–1.4 times the reciprocal intrinsic delay at $L_{\text{g}}=+20$% with 1.5–2.5 times the gate oxide thickness compared with the conventional MOSFETs with $X_{ j}=9.5$ nm. The feasibility of the CTE was experimentally demonstrated by the formation of electron inversion layers induced with Cs ions implanted into thermal oxide.
Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
2005-07-15