SoCデバイスのハードウェア・ソフトウェア協調設計に適した論理検証手法

概要

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This paper proposes a new logical verification method that generates a test bench automatically from a software program. It is suitable to develop a System-On-a-Chip (SoC) device by co-designing of hardware and software. In designing an LSI device designer have to supply its test bench and its input signal patterns for the logical verification manually, because there is no formalized technique of generating them automatically. In such situations, the high degree integration of a device realizes the SoC technology that implements processors, memories, etc. on one device. In order to solve the complicated description of test benches and input signal patterns required for the logical verification, we propose a description technique, called ALET language (an Assembly Language which makes it Easy to generate the Test bench), with which the designer can enter the hardware test items into the assembly language file of its software. In result, the more the test item increases, the more the description decreases. In the case of 100 test items, the amount of required inputs is reduced to approximately 6% of the former. Consequently, the testing becomes easier by using our proposing logical verification technique corresponding to high integration of a device.
社団法人電気学会の論文
2004-03-01