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The Ulsi Laboratory Mitsubishi Electric Corporation | 論文
- Features of SOI DRAM's and their Potential for Low-Voltage and/or Giga-Bit Scale DRAM's (Special Issue on ULSI Memory Technology)
- A Mixed-Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories
- A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme (Special Section on High Speed and High Density Multi Functional LSI Memories)
- Deep Submicron Field Isolation with Buried Insulator between Polysilicon Electrodes (BIPS) (Special Section on High Speed and High Density Multi Functional LSI Memories)
- A 90-MHz 16-Mb System Integrated Memory with Direct Interface to CPU
- Improved Array Architectures of DINOR for 0.5 μm 32 M and 64 Mbit Flash Memories (Special Section on High Speed and High Density Multi Functional LSI Memories)
- A Flexible Search Managing Circuitry for High-Density Dynamic CAMs (Speial Section on High Speed and High Density Multi Functional LSI Memories)
- Fully Self-Timing Data-Bus Architecture for 64-Mb DRAMs
- An Automatic Temperature Compensation of Internal Sense Ground for Subquarter Micron DRAM's(Special Issue on the 1994 VLSI Circuits Symposium)
- An Efficient Back-Bias Generator with Hybrid Pumping Circuit for 1.5-V DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Low Power and High Speed Data Transfer Scheme with Asynchronous Compressed Pluse Width Modulation for AS-Memory
- Cell-Plate-Line/Bit-Line Complementary Sensing (CBCS) Architecture for Ultra Low-Power DRAM's
- SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories
- A Blanket Source Line Architecture with Triple Metal for Giga Scale Memory LSIs (Special Issue on ULSI Memory Technology)
- Process and Device Technologies for Subhalf-Micron LSI Memory (Special Section on High Speed and High Density Multi Functional LSI Memories)