A 180 MHz Multiple-Registered 16 Mbit SDRAM with Flexible Timing Scheme (Special Section on High Speed and High Density Multi Functional LSI Memories)

概要

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A multiple-registered architecture is described for 180 MHz 16 Mbit synchronous DRAM. The proposed architecture realizes a flexible control of critical timings such as I/O line busy time and achieves an operation at 180MHz clock rate with area penalty of only 5.4 over the conventional DRAM.
社団法人電子情報通信学会の論文
1994-08-25