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System Devices Research Laboratories, NEC Corporation | 論文
- Breakdown Mechanisms and Lifetime Prediction for 90-nm-Node Low-Power HfSiON/SiO_2 CMOSFETs
- Influence of Charge Traps within HfSiON Bulk on Positive and Negative Bias Temperature Instability of HfSiON Gate Stacks
- 1.2nm HfSiON/SiON Stacked Gate Insulators for 65-nm-Node MISFETs
- Breakdown Mechanisms and Lifetime Prediction for 90nm-node Low-power HfSiON/SiO_2 CMOSFETs
- Influences of Traps within HfSiON Bulk on Positive- and Negative-Bias Temperature Instability of HfSiON Gate Stacks
- 1.2nm HfSiON/SiON stacked gate insulators for 65nm-node MISFETs
- C-4-22 液晶チューナブルミラーを用いたITLA対応小型波長可変レーザモジュール(C-4.レーザ・量子エレクトロニクス,一般講演)
- C-4-30 液晶チューナブルミラーを用いた高出力・広帯域外部共振器型波長可変レーザモジュール(C-4. レーザ・量子エレクトロニクス(波長可変レーザ), エレクトロニクス1)
- Solid-Electrolyte Nanometer Switch(Novel Device Architectures and System Integration Technologies)
- Highly Enhanced Speed and Efficiency of Si Nano-Photodiode with a Surface-Plasmon Antenna
- Si Nano-Photodiode with a Surface Plasmon Antenna
- A Metallurgical Prescription Suppressing Stress-induced Voiding (SIV) in Cu lines
- Mechanical Property Control of Low-k Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects
- MRAM Applications Using Unlimited Write Endurance(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
- Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode(Integrated Electronics)
- Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation(High-κ Gate Dielectrics)
- Suppression of Charges in Al_2O_3 Gate Dielectric and Improvement of MOSFET Performance by Plasma Nitridation
- 10-nm-Scale Pattern Delineation Using Calixarene Electron Beam Resist for Complementary Metal Oxide Semiconductor Gate Etching
- A 1-GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
- An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques (Interface and Interconnect Techniques, VLSI Design Technology in the Sub-100nm Era)