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Soongsil Univ. Seoul Kor | 論文
- A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
- A Precision Floating-Gate Mismatch Measurement Technique for Analog Application(Session 7B : Si IC and Circuit Technology)
- A Precision Floating-Gate Mismatch Measurement Technique for Analog Application(Session 7B : Si IC and Circuit Technology)
- A Physical-Based Modeling for Accurate Wide-Width LDMOS(Session 7B : Si IC and Circuit Technology)
- A Physical-Based Modeling for Accurate Wide-Width LDMOS(Session 7B : Si IC and Circuit Technology)
- A Non-snapback NMOS ESD Clamp Circuit using Gate-Coupled Scheme with Isolated Well in a Bipolar-CMOS-DMOS Process(Session 7B : Si IC and Circuit Technology)
- On-Chip Charged Device Model ESD Protection Design Method Using Very Fast Transmission Line Pulse System for RF ICs
- Analysis on the Behavior of a Low Voltage Triggered SCR ESD Clamp Circuit in Comparison between the Standard Transmission Line Pulse System and the Very Fast Transmission Line Pulse System
- Analysis on the Behavior of a Low Voltage Triggered SCR ESD Clamp Circuit in Comparison between the Standard Transmission Line Pulse System and the Very Fast Transmission Line Pulse System
- Selective Signal Combining for Effective BER Improvement in Noncoherent IR-UWB Systems
- Effective Selective Detection Scheme Based on Pulse Repetition for Coherent UWB Systems
- An Improved Timer-Based Location Management Scheme for Packet-Switched (PS) Mobile Communication Systems(Network)
- Novel Method of Interconnect Worstcase Establishment with Statistically-Based Approaches
- A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips(Electronic Circuits)
- Fast and Accurate Power Bus Designer for Multi-Layers High-Speed Digital Boards(Integrated Electronics)
- A Latchup-Free ESD Power Clamp Circuit with Stacked-Bipolar Devices for High-Voltage Integrated Circuits
- Low Voltage High-Speed CMOS Square-Law Composite Transistor Cell (Special Section on Analog Circuit Techniques and Related Topics)
- LV CMOS Analog VLSI Composite Cell Design and its Application to High Speed Multiplier
- Performance Analysis of the Mobility Anchor Point in Hierarchical Mobile IPv6(Mobile Multimedia Communications)
- A Simple Bit Allocation Scheme Based on Adaptive Coding for MIMO-OFDM Systems with V-BLAST Detector(Papers Selected from ITC-CSCC 2004)