スポンサーリンク
Semiconductor Leading Edge Technologies, Inc. (Selete), 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan | 論文
- Novel Air-gap Formation Technology Using Ru Barrier Metal for Cu Interconnects with High Reliability and Low Capacitance
- Fabrication of 70-nm-Pitch Two-Level Interconnects by using Extreme Ultraviolet Lithography
- Reconstruction of Latent Images from Dose-Pitch Matrices of Line Width and Edge Roughness of Chemically Amplified Resist for Extreme Ultraviolet Lithography
- Development of New Positive-Tone Molecular Resists Based on Fullerene Derivatives for Extreme Ultraviolet Lithography
- Fluorinated-Polymer Based High Sensitivity Extreme Ultraviolet Resists
- Resolution Enhancement for Beyond-22-nm Node Using Extreme Ultraviolet Exposure Tool
- High-Etching-Selectivity Barrier SiC ($k
- Resist Parameter Extraction from Line-and-Space Patterns of Chemically Amplified Resist for Extreme Ultraviolet Lithography
- Flare Impact and Correction for Critical Dimension Control with Full-Field Exposure Tool
- Galvanic Corrosion Control in Chemical Mechanical Polishing of Cu Interconnects with Ruthenium Barrier Metal Film
- Effect of Pattern Layout and Dissolved Oxygen in CO2 Rinse Water on Cu Corrosion during Post-Etch Cleaning
- Hole Mobility Enhancement Caused by Gate-Induced Vertical Strain in Gate-First Full-Metal High-$k$ P-Channel Field Effect Transistors Using Ion-Beam W
- Hybrid Electrochemical Mechanical Planarization Process for Cu Dual-Damascene Through-Silicon Via Using Noncontact Electrode Pad
- Evaluation of Chemical Gradient Enhancement Methods for Chemically Amplified Extreme Ultraviolet Resists
- Trench Sidewall Elimination Effect on Line-to-Line Leakage Current in Scalable Porous Silica ($k= 2.1$)/Cu Interconnect Structure
- Lithographic Performance of Extreme Ultravolet Full-Field Exposure Tool at Selete
- Extreme Ultraviolet Lithography Using Small-Field Exposure Tool: Current Status
- Application of Extreme Ultraviolet Lithography to Test Chip Fabrication
- Effect of Dissolved Oxygen on Cu Corrosion in Single Wafer Cleaning Process
- Origin of the Hole Current in n-type High-$k$/Metal Gate Stacks Field Effect Transistor in an Inversion State