スポンサーリンク
Nara Institute of Science and technology | 論文
- An Efficient Analysis of Worst Case Flush Timings for Branch Predictors
- An Efficient Analysis of Worst Case Flush Timings for Branch Predictors
- Reducing Processor Usage on Heavily-Loaded Network Servers with POSIX Real-Time Scheduling Control(System Programs)
- On the Effect of Scheduling in Test Generation
- A Variable-Length Coding Adjustable for Compressed Test Application
- An Adaptive Decompressor for Test Application with Variable-Length Coding
- Huffman-Based Test Response Coding
- Testing for the Programming Circuit of SRAM-Based FPGAs
- Learning to Acquire Whole-Body Humanoid Center of Mass Movements to Achieve Dynamic Tasks
- Sound reproduction based on multi-channel inverse filtering and WFS
- Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on τ^k-Notation(Complexity Theory)
- D-10-18 An Approach to Temperature Control During VLSI Test
- Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors
- Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability(Dependable Computing)
- Non-scan Design for Single-Port-Change Delay Fault Testability (特集:システムLSI設計とその技術)
- A DFT Selection Method for Reducing Test Application Time of System-on-Chips(SoC Testing)(Test and Verification of VLSI)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint(Test)(Dependable Computing)
- A Test Plan Grouping Method to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint
- Design for Two-Pattern Testability of Controller-Data Path Circuits
- Analyzing Path Delay Fault Testability of RTL Data Paths:A Non-Scan Approach (デザインガイヤ2000) -- (VLSIの設計/検証/テスト及び一般)