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Kyoto Univ. Kyoto‐shi Jpn | 論文
- High Channel Mobility in Inversion Layer of SiC MOSFETs for Power Switching Transistors
- On Finding a Fixed Point in a Boolean Network with Maximum Indegree 2
- Approximation Algorithms for Optimal RNA Secondary Structures Common to Multiple Sequences(Discrete Mathematics and Its Applications)
- Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- Limit Cycle of Induction Motor Drive and Its Control(Nonlinear Theory and its Applications)
- PA-1 大学の研究をどのように産業界に活かすか?
- AI-1-3 ディペンダブルVLSIプラットフォームへの挑戦(AI-1.デイベンダブルVLSIに向けて,依頼シンポジウム,ソサイエティ企画)
- A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
- A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
- A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era(Digital, Low-Power LSI and Low-Power IP)
- Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver(Analog Circuits and Related SoC Integration Technologies)
- Dynamic Channel Assignment Algorithms with Adaptive Array Antennas in Cellular Systems (Special Section on Multi-dimensional Mobile Information Networks)
- A Dynamic Timeslot Assignment Algorithm for Asymmetric Traffic in Multimedia TDMA/TDD Mobile Radio(Special Section on Fundamentals of Multi-dimensional Mobile Information Network)
- A Dynamic Channel Assignment Algorithm for Voice and Data Integrated TDMA Mobile Radio (Special Section on Mutli-dimensional Mobile Information Network)
- A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era(Electronic Circuits)
- 柔軟な信頼性を実現する粗粒度再構成可能アーキテクチャの検討(ディペンダブル設計,デザインガイア2008-VLSI設計の新しい大地)
- Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(VLSI Design and CAD Algorithms)
- Experimental Study on Cell-Base High-Performance Datapath Design
- Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
- Special Section on Analog Circuit Techniques for System-on-Chip Integration