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Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U | 論文
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)
- Design and Simulation of Asymmetric MOSFETs
- Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-5Onm Low-Power and High-Speed MOSFET Design(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- Reverse-Order Source/Drain with Double Offset Spacer (RODOS) for Sub-50nm Low-Power and High-Speed MOSFET Design (AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Side-Gate Design for 50nm Electrically Induced Source/Drain MOSFETs
- Side-gate Length Optimization for 50nm Induced Source/Drain MOSFETs
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As^+_2 Low Energy Implantations
- 70nm NMOSFET Fabrication with 12nm n^+-p Junctions Using As_2^+ Å Low Energy Ion Implantations
- Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL)
- Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Electron devices: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Design and simulation of single hole transistor with tunneling barrier formed by fixed charge (Silicon devices and materials: 第15回先端半導体デバイスの基礎と応用に関するアジア・太平洋ワークショップ(AWAD2007))
- Properties of the p^+ poly-Si Gate Fabricated Using the As Preamorphization Method
- As Preamorphization of the Predeposited Amorphous Si Layer for the Formation of the Silicided Ultra Shallow p^+-n Junction
- Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications
- Metal FEAs Fabricated with Local Oxidation of Polysilicon for Large-Area Display Applications
- Fiber-Optic Separation and Compression of Gain-Switched Multimode Semiconductor Laser Pulses
- A New 1T DRAM Cell : Cone Type 1T DRAM Cell
- Effects of Conductive Defects on Unipolar RRAM for the Improvement of Resistive Switching Characteristics
- Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)
- Comparative Study on Top- and Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors