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Inter-university Semiconductor Research Center And School Of Electrical Engineering Seoul National U | 論文
- Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
- Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory
- 3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
- Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
- Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design
- Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme
- Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
- A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology
- Indium Doped nMOSFETs and Buried Channel pMOSFETs with n^+ Polysilicon Gate
- Channel Doping Engineering with Indium as an Alternative p-Type Dopant
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Nanoscale Poly-Si Line Formation and Its Uniformity
- Design and Simulation of Asymmetric MOSFETs(Junction Formation and TFT Reliability,Fundamentals and Applications of Advanced Semiconductor Devices)
- Novel Gate-All-Around MOSFETs with Self-Aligned Structure
- Synchronous Mirror Delay for Multi-phase Locking
- Synchronous Mirror Delay for Multi-phase Locking
- Nanoscale Poly-Si Line Formation and Its Uniformity (2001 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices(AWAD 2001))
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 : Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices)
- Junction Leakage Characteristics of Shallow Trench Isolation (STI) with Nitrogen Pile-Up Sidewall Oxide(AWAD2003 (Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices))
- Design and Simulation of Asymmetric MOSFETs(Session 7A Silicon Devices IV,AWAD2006)