スポンサーリンク
Department of Communication and Computer Engineering, Graduate School of Informatics, Kyoto University, Kyoto 606-8501, Japan | 論文
- Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells
- Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling(Analog Circuits and Related SoC Integration Technologies)
- Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line(Interconnect,VLSI Design and CAD Algorithms)
- Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling(Selected Papers from the 17th Workshop on Circuits and Systems in Karuizawa)
- Representative Frequency for Interconnect R(f)L(f)C Extraction(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- A 90nm 48×48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations(Low-Power and High-Performance VLSI Circuit Technology,VLSI Technology toward Frontiers of New Market)
- A 90nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations(Digital,Low-Power, High-Speed LSIs and Related Technologies)
- Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver(Analog Circuits and Related SoC Integration Technologies)
- Experimental Study on Cell-Base High-Performance Datapath Design(IP Design)(VLSI Design and CAD Algorithms)
- Timing Analysis Considering Spatial Power/Ground Level Variation(Physical Design,VLSI Design and CAD Algorithms)
- Manufacturability-Aware Design of Standard Cells(Physical Design,VLSI Design and CAD Algorithms)
- Statistical Gate Delay Model for Multiple Input Switching
- Timing Analysis Considering Temporal Supply Voltage Fluctuation
- Successive Pad Assignment for Minimizing Supply Voltage Drop(Power/Ground Network, VLSI Design and CAD Algorithms)
- An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity
- A Memory-Based Parallel Processor for Vector Quantization:FMPP-VQ (Special Issue on New Concept Device and Novel Architecture LSIs)
- A Current Mode Cyclic A/D Converter with Submicron Processes (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
- Crosstalk Noise Estimation for Generic RC Trees(Parasitics and Noise)(VLSI Design and CAD Algorithms)
- Effects of On-Chip Inductance on Power Distribution Grid(VLSI Design and CAD Algorithms)