Cao Peng | National ASIC system and research engineering center, Southeast University
スポンサーリンク
概要
関連著者
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Cao Peng
National ASIC system and research engineering center, Southeast University
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Shi Longxing
National ASIC Center, Southeast University
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Yang Jun
National Asic System Engineering Research Center Southeast University
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Zhu Min
Institute Of Microelectronics Tsinghua University
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Liu Leibo
Institute Of Microelectronics Tsinghua University
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Wei Shaojun
Institute Of Microelectronics Tsinghua University
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Cao Peng
National Asic System Engineering Research Center Southeast University
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Cao Peng
National Asic System Engineering Technology Research Center Southeast University
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Shan Weiwei
National ASIC system and research engineering center, Southeast University
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NGUYEN Hung
National ASIC system Engineering Research Center, Southeast University
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WANG Xue-Xiang
National ASIC system Engineering Research Center, Southeast University
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Wang Chao
National Asic System Engineering Technology Research Center Southeast University
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Zhang Xiao
Shanghai Jiaotong University
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Shi Longxing
National Asic System Engineering Technology Research Center Southeast University
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Shi Longxing
National Asic System Engineering Research Center Southeast University
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CAO Peng
National ASIC System Engineering Technology Research Center, Southeast University
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LIU Xinning
National ASIC system Engineering Research Center, Southeast University
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MEI Chen
National ASIC system Engineering Research Center, Southeast University
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Mei Chen
National Asic System Engineering Research Center Southeast University
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Liu Xinning
National Asic System Engineering Research Center Southeast University
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ZHU Min
Institute of Microelectronics, Tsinghua University
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CAO Peng
National ASIC system Engineering Research Center, Southeast University
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WEI Shaojun
Institute of Microelectronics, Tsinghua University
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YANG Jun
National ASIC system Engineering Research Center, Southeast University
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LIU Bo
National ASIC system Engineering Research Center, Southeast University
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Fu Xingyuan
National ASIC System Engineering Research Center, Southeast University
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Gu Haolin
National ASIC system and research engineering center, Southeast University
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Li Bo
Electrical and Computer Engineering Department, University of Maryland
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Wu Xiaoqing
National ASIC system and research engineering center, Southeast University
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Jin Haikun
National ASIC system and research engineering center, Southeast University
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Guo Yintao
National ASIC system and research engineering center, Southeast University
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GAO Gugang
National ASIC System Engineering Technology Research Center, Southeast University
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YIN Shouyi
National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University
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WANG Yansheng
National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University
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LIU Leibo
National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University
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ZHU Min
National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University
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WEI Shaojun
National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University
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Zhang Xiao
Shanghai Information Security Testing Evaluation and Certification Center
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YANG Jun
National ASIC System Engineering Research Center, Southeast Univ.
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YANG Jun
National ASIC System Engineering Technology Research Center, Southeast University
著作論文
- Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm
- Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications
- Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications
- Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC
- Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip
- An improved timing monitor for deep dynamic voltage scaling system
- The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture
- VLSI Design of a Reconfigurable S-box Based on Memory Sharing Method
- Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip