Deep Submicron CMOS Technology Using Top-Edge Round STI and Dual Gate Oxide for Low Power 256M-Bit Model DRAM
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2003-04-30
著者
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Kim Hyeong
School of Materials Science and Engineering, Seoul National University
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Lee Chihoon
School Of Materials Science And Engineering Seoul National University
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Park Donggun
Dram Process Architecture Team Memory Product & Technology Division Samsung Electronics Co. Ltd.
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JO Namhyuk
DRAM Process Architecture Team, Memory Product & Technology Division, Samsung Electronics Co., Ltd.
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HWANG Chanseong
DRAM Process Architecture Team, Memory Product & Technology Division, Samsung Electronics Co., Ltd.
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LEE Wonshik
DRAM Process Architecture Team, Memory Product & Technology Division, Samsung Electronics Co., Ltd.
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Jo Namhyuk
Dram Process Architecture Team Memory Product & Technology Division Samsung Electronics Co. Ltd.
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Lee Wonshik
Dram Process Architecture Team Memory Product & Technology Division Samsung Electronics Co. Ltd.
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Hwang Chanseong
Dram Process Architecture Team Memory Product & Technology Division Samsung Electronics Co. Ltd.
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Kim Hyeong
School Of Materials Science And Engineering Seoul National University
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Kim Hyeong
School Of Materials Science & Engineering Seoul National University
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Kim Hyeong
School Of Electrical And Electronics Engineering Chung-ang University
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