Analysis of Plasma Wall Reactions Using Virtual Optical Emission Spectrometry Signal during Dielectric Etching
スポンサーリンク
概要
- 論文の詳細を見る
We confirmed that the SiN etch rate uniformity depends on not only the spatial distribution of the H radical density which is strongly affected by loss rates on chamber walls but also time-dependence of the loss rates. We developed a numerical simulation method for plasma–wall reactions to predict both the spatial distribution of the H radical density and the optical emission intensity observed from the view port during dielectric etching. In comparing experimental optical emission spectrometer (OES) data with virtual OES (our simulation), loss probabilities of the H radical on the Si, SiO2, and C–F polymer surfaces were estimated to be 0.5, 0.06, and 0.1, respectively. We successfully predicted SiN etch rates under various wall conditions by considering the spatial distribution and time-dependence of the loss probabilities.
- 2010-08-25
著者
-
Kawashima Atsushi
Semiconductor Technology Development Division, SBG, CPDG, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
-
Fukasawa Masanaga
Semiconductor Technology Development Division, Core Device Development Group, R&D Platform, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
-
Tatsumi Tetsuya
Semiconductor Technology Development Division, Core Device Development Group, R&D Platform, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
-
Tatsumi Tetsuya
Semiconductor Technology Development Division, SBG, CPDG, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
-
Kuboi Nobuyuki
Semiconductor Technology Development Division, SBG, CPDG, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
-
Oshima Keiji
Semiconductor Technology Development Division, SBG, CPDG, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
-
Nagahata Kazunori
Semiconductor Technology Development Division, SBG, CPDG, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
-
Tatsumi Tetsuya
Semiconductor Technology Development Division, Advanced Device Technology Platform, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
-
Fukasawa Masanaga
Semiconductor Technology Development Division, Advanced Device Technology Platform, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan
-
TATSUMI Tetsuya
Semiconductor Technology Development Division, Advanced Device Technology Platform, Sony Corporation
-
KUBOI Nobuyuki
Semiconductor Technology Development Division, Advanced Device Technology Platform, Sony Corporation
関連論文
- Prediction of Fluctuations in Plasma–Wall Interactions Using an Equipment Engineering System
- Si Recess of Polycrystalline Silicon Gate Etching: Damage Enhanced by Ion Assisted Oxygen Diffusion
- Analysis of GaN Damage Induced by Cl2/SiCl4/Ar Plasma
- Optical and Electrical Characterization of Hydrogen-Plasma-Damaged Silicon Surface Structures and Its Impact on In-line Monitoring
- Analysis of Plasma Wall Reactions Using Virtual Optical Emission Spectrometry Signal during Dielectric Etching
- Numerical Simulation Method for Plasma-Induced Damage Profile in SiO Etching
- Reducing Damage to Si Substrates during Gate Etching Processes
- Wavelength Dependence of Photon-Induced Interface Defects in Hydrogenated Silicon Nitride/Si Structure during Plasma Etching Processes
- Wavelength Dependence of Photon-Induced Interface Defects in Hydrogenated Silicon Nitride/Si Structure during Plasma Etching Processes (Special Issue : Dry Process)
- Modeling and Simulation of Plasma-Induced Damage Distribution during Hole Etching of SiO_2 over Si Substrate by Fluorocarbon Plasma