Development of Hard Mask Process on Magnetic Tunnel Junction for a 4-Mbit Magnetic Random Access Memory
スポンサーリンク
概要
- 論文の詳細を見る
To enlarge the read margin of magnetic random access memory (MRAM), we developed a SiO2/Si3N4 hard mask process for magnetic tunnel junction (MTJ) stack patterning. This process can protect MTJ materials from oxidation during the resist removal process and reduces the distribution of MTJ resistance for 0.32-μm-wide bits on an 8-in.-diameter wafer more than the conventional process does. We also developed process integration for 4-Mbit toggle MRAMs: the read margin for 4-Mbit reached nearly $18\sigma$.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2007-07-15
著者
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KASAI Naoki
System Devices Research Laboratories, NEC Corporation
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Hada Hiromitsu
System Devices And Fundamental Research Nec Corporation
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MUKAI Tomonori
System Devices Research Laboratories, NEC Corporation
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Nagahara Kiyokazu
System Devices Research Laboratories, NEC Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa 229-1198, Japan
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Yoda Hiroaki
Center for Semiconductor Research and Development, Toshiba Corporation, Yokohama 235-8522, Japan
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Yoda Hiroaki
Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Yokohama 253-8522, Japan
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Asao Yoshiaki
Center for Semiconductor Research and Development, Toshiba Corporation, Yokohama 235-8522, Japan
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Asao Yoshiaki
Center for Semiconductor Research and Development, Semiconductor Company, Toshiba Corporation, Yokohama 253-8522, Japan
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Nagahara Kiyokazu
System Devices Research Laboratories, NEC Corporation, Sagamihara, Kanagawa 229-1198, Japan
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Hada Hiromitsu
System Devices Research Laboratories, NEC Corporation, Sagamihara, Kanagawa 229-1198, Japan
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Ishiwata Nobuyuki
System Devices Research Laboratories, NEC Corporation, Sagamihara, Kanagawa 229-1198, Japan
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Mukai Tomonori
System Devices Research Laboratories, NEC Corporation, Sagamihara, Kanagawa 229-1198, Japan
関連論文
- MRAM Applications Using Unlimited Write Endurance(Next-Generation Memory for SoC,VLSI Technology toward Frontiers of New Market)
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- Characterization of Ferroelectric Domain Behavior in MOCVD-PZT Capacitors for CMVP FeRAMs
- High-Performance and Damage-Free Magnetic Film Etching using Pulse-Time-Modulated Cl2 Plasma
- Magnetically Damage-free Etching of MTJ Film for Future 0.24-μm-rule MRAMs
- Switching-Field Stabilization against Effects of High-Temperature Annealing in Magnetic Tunnel Junctions using Thermally Reliable NixFe100-x/Al-Oxide/Ta Free Layer
- Ion Beam Etching Technology for High-Density Spin Transfer Torque Magnetic Random Access Memory
- Development of Hard Mask Process on Magnetic Tunnel Junction for a 4-Mbit Magnetic Random Access Memory