Scalable Wordline Shielding Scheme using Dummy Cell beyond 40 nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell
スポンサーリンク
概要
- 論文の詳細を見る
A scalable wordline shielding scheme using dummy cell in NAND flash memory is presented to eliminate abnormal disturb of edge memory cell which causes to degradation of NAND flash performance. The proposed NAND flash is also able to improve more NAND scaling compared to conventional NAND string beyond sub-40 nm technology node. By using a proposed program scheme which includes an optimized bias voltage and adjusted $V_{\text{th}}$ of dummy cell, almost abnormal disturbance of edge memory cell is removed and over 58% capacitive coupling noise between select transistor and edge memory cell can be reduced from both simulation and experimental results which used 63 nm NAND flash technology. The proposed NAND flash also improves $V_{\text{th}}$ distribution of memory cell by providing almost equal operation conditions for all memory cells in NAND string.
- 2007-04-30
著者
-
Kim Kinam
Semiconductor R & D Center Memory Division Semiconductor Business Samsung Electronics Co. Ltd.
-
Lee Seungchul
Semiconductor R&d Center Cae Team
-
Choi Jungdal
Semiconductor R&D Center, Memory Business, Samsung Electronics Co., Ltd., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do 449-711, Korea
-
Park Ki-Tae
Semiconductor R&D Center, Memory Business, Samsung Electronics Co., Ltd., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do 449-711, Korea
-
Sel Jong-Sun
Semiconductor R&D Center, Memory Business, Samsung Electronics Co., Ltd., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do 449-711, Korea
-
Park Ki-Tae
Semiconductor R&D Center, Memory Business, Samsung Electronics Co., Ltd., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do 449-711, Korea
-
Kim Kinam
Semiconductor R&D Center, Memory Business, Samsung Electronics Co., Ltd., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do 449-711, Korea
-
Sel Jong-Sun
Semiconductor R&D Center, Memory Business, Samsung Electronics Co., Ltd., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do 449-711, Korea
-
Lee SeungChul
Semiconductor R&D Center, Memory Business, Samsung Electronics Co., Ltd., San #24, Nongseo-Dong, Kiheung-Gu, Yongin-City, Kyunggi-Do 449-711, Korea
関連論文
- Self-Aligned Local Channel Implantation Using Reverse Gate Pattern for Deep Submicron Dynamic Random Access Memory Cell Transistors
- Cell Transistor Design Using Self-Aligned Local Channel Implant(SALCI) for 4Gb DRAMs and Beyond
- Current Development Status and Future Challenge of FeRAM Technologies
- Deep Trench Isolation for Pixel Crosstalk Suppression in Active Pixel Sensor with 1.7μm pixel pitch
- A Novel NAND Flash Technology with Selective Epitaxial Growth Plug Structure for the Improvement in HV Transistor Breakdown Voltage
- Scalable Wordline Shielding Scheme using Dummy Cell beyond 40nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell
- Dynamic Data Retention Degradation in FD-SOI DRAM Cells Due to Source-Induced Charge Accumulation(SICA) Effect
- Deep Trench Isolation for Crosstalk Suppression in Active Pixel Sensors with 1.7 μm Pixel Pitch
- Source-Bias Dependent Charge Accumulation in P^+-Poly Gate SOI Dynamic Random Access Memory Cell Transistors
- Scalable Wordline Shielding Scheme using Dummy Cell beyond 40 nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell